1. Field of the Invention
This invention relates to a semiconductor package and a method of fabrication thereof or, in particular, to a semiconductor package and a method of fabrication thereof in which terminals for external connection or terminals for mounting a semiconductor element are formed as bumps protruded from the package surface, each bump being filled with an insulating resin and covered with a metal. The invention further relates to a semiconductor device and a method of fabrication thereof using the semiconductor package.
2. Description of the Related Art
The external connection terminals of the conventional a semiconductor package are formed of a multiplicity of balls for the ball grid array (BGA) package as shown in FIG. 1 and a multiplicity of pins for the pin grid array (PGA) package as shown in FIG. 2.
Specifically, FIG. 1 shows the structure of the conventional BGA package, wherein the upper surface of a package 1 constitutes a semiconductor element-mounting surface, and the lower surface thereof constitutes an external connection terminal side, and wherein a semiconductor element 2 electrically connected to each terminal is mounted on the semiconductor element-mounting surface and the external connection terminals are formed as a multiplicity of balls 3 protruded downward.
FIG. 2 shows the structure of the conventional PGA package in which, as in FIG. 1, the upper surface of the package 1 makes up a semiconductor element-mounting surface, and the lower surface thereof makes up an external connection terminal side on which the semiconductor element 2 electrically connected to each terminal is mounted on the semiconductor element-mounting surface. The external connection terminal side, on the other hand, is configured of a multiplicity of pins 4 protruded downward.
In the case where the solder balls 3 are used as external connection terminals as described above, the terminals are normally formed of a solder containing lead. Also, in the case where the pins 4 are used as the external connection terminals, the portion where the pins 4 are mounted is normally formed of solder containing lead.
From the viewpoint of environment protection, however, demand has recently risen for a connection method in which a semiconductor element is mounted or connected and the external connection terminals coupled with other parts without using a solder containing lead.
As a conventional technique related to this invention, JP-A 9-283925 proposes a BGA semiconductor device including semiconductor elements and mounted in an external circuit, which makes possible a fine pitch of the ball grid array and a reduced package size, while at the same time realizing an improved connection reliability. In the conventional semiconductor device disclosed by this patent publication, depressions for solder bumps of the ball grid array are formed on one surface of a metal plate, and after forming a solder layer and a conductor metal layer by electrolytic plating in the depressions, as many insulating layers and wiring layers as required are stacked on the metal plate thereby to form a multilayer wiring circuit board. After thus mounting the semiconductor element and sealing it with resin, the metal plate is etched off to form the solder bumps.
According to this method, the depressions for solder bumps are formed by etching a metal plate. Therefore, the solder bumps are not substantially varied in shape, and the solder shape remains stable after reflow, thereby contributing to a finer pitch.
JP-A 2004-64082, on the other hand, discloses a configuration in which, in order to realize a fine wiring arrangement with a high density corresponding to an increased number and a smaller pitch of the semiconductor device terminals, wiring is laid on the upper surface of an insulating layer constituting an independent single layer, and an electrode is formed on the lower surface of the insulating layer. The side periphery of the upper end of the electrode is in contact with the insulating layer and the lower end thereof is projected from the lower surface of the insulating layer without contacting the insulating layer. This electrode and the wiring are electrically connected to each other through a via hole formed in the insulating layer, while a support member is arranged on the surface of the insulating layer.
JP-A 2004-64082 also discloses a configuration in which a resist layer having an opening pattern corresponding to the electrode pattern is formed on a substrate, and with the resist layer as a mask, the substrate is etched thereby to form recesses corresponding to the opening pattern of the resist layer on the upper surface of the substrate. After that, a metal is deposited in the recesses and the opening pattern thereby to form an electrode pattern.
According to JP-A 9-283925, the solder bumps are not varied in shape and a fine pitch can be achieved by stabilizing the solder shape after reflow. In view of the fact that the solder of the solder bumps normally contains lead, however, the environmental problem is not solved due to the use of lead in the solder bumps as external connection terminals or semiconductor element connection terminals.
The conventional technique disclosed in JP-A 2004-64082 does not solve the environmental problem posed by the use of lead in the external connection terminals or the semiconductor element connection terminals of a semiconductor package.